The present invention relates generally to QAM quadrature amplitude modulation) demodulators, and more specifically to a control circuit for gain-controlled amplifiers which respectively amplify the in-phase and quadrature-phase components of a QAM signal.
According to a prior art QAM demodulator as shown in FIG. 1, in-phase P-channel baseband signal and a quadrature phase Q-channel baseband signal are applied respectively to gain-controlled amplifiers 1P and 1Q converted to digital signals by A/D converters 2P and 2Q. The digital signals from A/D converters 2P and 3P are applied to threshold decision circuits 3P and 3Q, respectively, in each of which a decision is made on whether the respective signal is higher or lower than a signal point of the signal constellation of the QAM signal to produce data bits and an error bit. Both data and error bits of the P- and Q-channel signals are applied to controllers 4P and 4Q, respectively, to derive gain control signals for coupling to the respective gain-controlled amplifiers. If the incoming signal is a 128-QAM signal, each threshold decision circuit produces a set of four data bits and one error bit in response to each signal point. The output of each threshold decision circuit is applied to the associated controller in which the signal constellation of the incoming signal is divided into regions A, B and C as shown in FIG. 2. The controller makes a decision in favor of a logical 1 if a given signal point belongs to outermost regions A or in favor of a logical 0 if it belongs to innermost region B. If the signal point lies within intermediate regions C, the decision is made in favor of the binary state of the previous time slot. The gain of each amplifier is reduced when the average number of logical 1's increases and increased when the average number of logical 0's decreases, and by doing this the gain is converged to the reference signal points. The other function of each gain controlled amplifier is to compress the dynamic range of the respective baseband signal so that it does not exceed beyond the specified dynamic range of the input to the associated A/D converter even if the waveform of the signal is severely distorted during propagation. The dynamic range of the digital output from each A/D converter needs to be expanded to the original range before being compared with the thresholds of each decision circuit 3.
However, the number of the innermost signal points lying on the lines that define boundaries between regions B and C is greater than the number of the outermost signal points lying on the lines defining boundaries between regions A and C. Since the probability of occurrences of a logical 1 is equal to that of a logical 0 in the signal constellation of a 128-QAM signal, the ratio of the likelihood of each gain control signal assuming a logical 1 to the likelihood of it assuming a logical 0 is 8:12 when the received signal points are converged to the reference signal points. Although the likelihood of occurrences is in imbalance between 1's and 0's, an input level fluctuation will cause logical 1's and 0's to occur at different rates as long as the feedback operation is in the process of convergence to the reference signal points so that the gain is quickly adjusted to counteract the fluctuation. If the feedback operation is in a process from a diverged to a converged state, on the other hand, the gain of each AGC amplifier is raised to a level higher than the range of values normally used during the converged state so that the occurrences of logical 1's and 0's are made to be equal to each other. However, under such circumstances the imbalance between 1's and 0's causes the feedback loop to enter a state of instability, and difficulty results for restoring the state of convergence.